Lowering the power consumption and increasing the overall power efficiency is one of the top priorities for the semiconductor industry. There are many parallel paths that the industry is following up on (e.g., lowering the power supply voltage with decreasing node, adjustable supply voltage depending on the usage, subthreshold computing, and power gating).
Power gating is an established practice in system on chip (SoC) design. It refers to the application of switches in an integrated circuit (IC) design. These switches may be configured to switch OFF the current to parts of the IC in order to save power. FIG. 1 shows an integrated circuit comprising different units (e.g., μcore unit 110 and memory unit 120) implemented in the front-end-of-line (FEOL) portion of the IC. FIG. 1 also shows a power gating switch 130 that allows switching OFF one or more of the units in the IC. A plurality of power gating switches may allow obtaining a distributed power gating. Such a combination of units that can be switched OFF separately is also referred to as a power isle. In some examples, FEOL transistors at the periphery of the SoC may be used to switch OFF power isles containing a large number of transistors, for instance at least 105 transistors. Switching OFF a power isle of the IC during its idle time may reduce the static power consumption, which may be caused by leakage of such a power isle.
European Patent App. No. EP2884542 discloses an IC device with a power gate transistor implemented in the back end of line (BEOL) to reduce static power consumption.
In some examples, power gating may result in significant energy savings; however, only on the condition that the usage frequency is low (e.g., in a mobile SoC with usage frequency of less than 5%) and on the condition that the idle times are significantly longer than the time required to power up the power isles.